| 2022-ROGE-69664 | |
| Researchers at Purdue University have proposed a new design for CPUs that seeks to improve end-to-end efficiency. This new design attempts to overcome the slowing of Moore's law, wafer shortages, increasing power consumptions, and environmental impacts. Further reducing the size of transistors has also been difficult. The Purdue researchers' technology seeks to enhance computing power by batching similar data from the same source code and processing it as a single instruction. This is done by using a new device called a request processing unit (RPU). The researchers combine the benefits of the efficiency and memory scalability of GPUs with the latency optimization of CPUs. This technology has large potential for use in cloud microservices. Technology Validation: The researchers' method achieves 100% accuracy to determine the correct reconvergence points for GPGPU workloads and up to 94% for CPU SPECint workloads. Related Publication: M. Khairy, A. Alawneh, A. Barnes and T. G. Rogers, "SIMR: Single Instruction Multiple Request Processing for Energy-Efficient Data Center Microservices," 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, IL, USA, 2022, pp. 441-463, doi: 10.1109/MICRO56248.2022.00040. Advantages: - High throughput - Lower end-to-end tail latency - Reduced power consumption Applications: - Data centers - Integrated into current CPU designs |
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Nov 30, 2022
Utility-Gov. Funding
United States
(None)
(None)
Aug 19, 2022
Provisional-Gov. Funding
United States
(None)
(None)
Feb 8, 2022
Provisional-Gov. Funding
United States
(None)
(None)
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Purdue Office of Technology Commercialization The Convergence Center 101 Foundry Drive, Suite 2500 West Lafayette, IN 47906 Phone: (765) 588-3475 Fax: (765) 463-3486 Email: otcip@prf.org |
