|Advancements and increased scaling in technology have continued to increase energy dissipation in charging/discharging global interconnect wire capacitances. There are numerous methods for dealing with this issue, but all have shortcomings such as, excess power consumption and delay and performance degradation. An alternative Spin-Torque (ST) technique has been proposed as a potentially energy efficient method; however, this method does not use repeaters or buffers in the line to minimize the overall delay. There is need of an improved method that accommodates buffering schemes for delay minimization in complementary metal-oxide-semiconductor (CMOS) technology.
Researchers at Purdue University have developed a low voltage/current interconnect architecture using both ST sensors at the receiver and ST-buffers in specific sections of the wiring. These modifications change the resistance in the wiring, which would make the circuit more efficient compared to existing technologies by greatly reducing delay, energy consumption, as well as improving bandwidth. In addition, complexity of operation is reduced, and the system has better noise immunity. The enhanced energy-delay performance of the technology would be innovated into CMOS designs for both global on-chip and off-chip communication.
-Reduced complexity of operation
-Better noise immunity
-Improved delay and bandwidth
-Global on/off-chip communication
Oct 23, 2018
Oct 24, 2017
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