|High channel resistance in silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) results from low electron mobility and poor oxide-SiC interface quality. A post-oxidation anneal, typically in a nitric oxide ambient, addresses this problem. Other common approaches include other anneal ambients, such as nitrous oxide, nitrogen plasma, POCI3, etc., resulting in improvements of ~10x over as grown thermal oxide, have made practical SiC MOSFETs possible. However, the resulting channel mobility is still only approximately 5 percent of the bulk SiC electron mobility. Many important applications require lower voltages. SiC channel resistance limits MOSFET performance in this voltage range.
Purdue University researchers have developed a SiC surface by depositing gate oxide vs. traditional thermally grown oxide, use a combination of high temperature hydrogen etching to clean the SiC surface, and either a hydrogen or silicon oxynitride termination structure to preserve and protect the surface prior to atomic layer deposition of the oxide. This technology removes oxidation from the process, which is likely responsible for the low mobility of such structures. When using a deposited oxide, the surface becomes the interface. This technique provides an ideal surface on which to deposit the gate oxide, resulting in an improvement in interface quality and reduction in channel resistance.
-Provides solution for low channel mobility
-Improved interface quality
-Reduction in channel resistance
-Low voltage applications:
-Hybrid electric vehicles
-Server farm power supplies
-Renewable energy power conversion
Feb 12, 2018
Feb 10, 2017
Purdue Office of Technology Commercialization
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