|In power double-diffused metal-oxide-semiconductor field-effect transistors (DMOSFETs) fabricated in the silicon carbide SiC process, it is difficult to find a process that yields consistent results without slightly hindering the performance of the device. In order to reduce misalignment errors, the source contacts are designed slightly larger than necessary to allow for adjustments. These misalignment errors can lead to large contact resistances.
Purdue University researchers have developed a novel design for DMOSFETs with self-aligning source contacts, which reduce the size of the source contacts and consequently reduces the specific-on resistance of the device.
-Reduces specific on-resistance
Apr 23, 2009
Oct 11, 2011
Apr 23, 2008
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