Parallel Algorithms for Sparse Matrix Simulations

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Due to the increasing complexity of integrated circuits (ICs), computer software for IC design requires high-speed computer hardware. In many cases, supercomputers with parallel processors are used to decrease the time required to perform the system-intensive calculations.

Purdue University researchers have developed a novel parallel divide-and-conquer algorithm for the general solution of large linear systems that arise in IC design simulations. The algorithm allows for large-scale problems that intensely consume memory or are overly computationally intensive to be solved through the use of distributed computing, reducing the intensive load on a single processor, increasing performance of the entire system.

Advantages:
-Faster than current processes
-Compatible with multiple processor systems

Potential Applications:
-Computer Technology
-Software
Dec 10, 2012
CON-Patent
United States
8,745,563
Jun 3, 2014

Aug 9, 2010
DIV-Patent
United States
8,336,014
Dec 18, 2012

Nov 6, 2006
Utility Patent
United States
7,774,725
Aug 10, 2010

Nov 30, 2005
Provisional-Patent
United States
(None)
(None)

Nov 4, 2005
Provisional-Patent
United States
(None)
(None)
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