Low-Power Synthesis Technique with Dynamic Supply Gating

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As electronics get smaller, the demand for smaller complementary metal oxide semiconductor (CMOS) devices increases. However, smaller CMOS devices produce undesired effects such as increased subthreshold leakage current. In the past, these problems have been offset by reducing the supply voltage, which results in significant degradation in performance.

Purdue University researchers have developed a novel method to reduce switching power dissipating and subthreshold leakage current in CMOS integrated circuits.

Advantages:
-Dramatic power reduction without performance sacrifice
-Extends battery life of portable electronic devices
-Improves reliability of integrated circuits
-Increased scope of applications for nanometer technologies

Potential Applications:
-Circuitry
-Devices
Jun 9, 2006
Utility Patent
United States
7,454,738
Nov 18, 2008

Jun 10, 2005
Provisional-Patent
United States
(None)
(None)
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