Polymer-Based Heterogeneous Integration Technology

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One of the most critical levels of electronic packaging is that of packaging and interconnection of integrated circuits and semiconductor devices. Using available technology, there is typically a minimum pitch size for reliable connection between a metallization pad on the chip and the one on the package. This places limitations on the density of interconnections coming out of the chip and introduces additional parasitic capacitance due to the large contact area required. Therefore, driver circuits are often needed to support input/output pads for fast operation.

Researchers at Purdue University have developed a new approach to remove the packaging and bulky passive elements from expensive active chips and fabricate them within a less expensive carrier substrate; therefore, reducing the cost of the integrated system.

Advantages:
-Reduces size and cost
-Decreases parasitic capacitance
-More reliable and efficient

Potential Applications:
-Materials
-Manufacturing
-Microelectronics
-Nanoelectronics
Jan 27, 2006
Utility Patent
United States
7,473,579
Jan 6, 2009

Nov 26, 2008
DIV-Patent
United States
(None)
(None)

Jan 31, 2005
Provisional-Patent
United States
(None)
(None)
Purdue Office of Technology Commercialization
1801 Newman Road
West Lafayette, IN 47906

Phone: (765) 588-3475
Fax: (765) 463-3486
Email: otcip@prf.org